Mixed Compact and Behavior Modeling Using AHDL Verilog-A

The way from the compact model development to implementation into a commercial circuit simulator is often time consuming. Moreover, it is not always straightforward how to implement behavior models in SPICE-like simulators. In this paper, a capability of the analog hardware description language (AHDL) Verilog-A to handle state-of-the-art compact bipolar transistor modeling mixed with behavioral substrate coupling modeling has been demonstrated. Introduction The Verilog-A is a high-level language developed to describe the structure and behavior of analog systems and their components (1). It is an extension to the IEEE 1364 Verilog HDL specification for digital design. The analog systems are described in Verilog-A in a modular way using hierarchy and different levels of modeling complexity. The motivation is to invest in a new higher level of abstraction in analog design and its combination with the digital one. The basic programming unit for the structural and behavioral description of the analog systems in Verilog-A is a module. The analog system structure is defined through the module’s input and output signals and their connections. On the other hand, the sequence of mathematical equations is employed at the core of the module to describe its behavior. It is also possible to control the equations by a set of parameters that can be passed to the module at the moment of its instantiation into the analog system. With these features, Verilog-A language represents an excellent environment for rapid development and verification of compact and behavioral modeling ideas in the commercial circuit simulators. In order to practically verify capabilities of Verilog-A to serve as a framework for mixed compact and behavioral model developments we have implemented the bipolar transistor compact model Mextram Level 504 directly following the model description in the Philips documentation (2). Since the present Mextram release does not include substrate model, it is added here in the form of a Verilog-A behavioral model based on the Laplace transfer function. Compact Model Implementation and Testing The Verilog-A Mextram 504 implementation has been tested using the Cadence circuit simulator Spectre equipped with the Verilog-A interface. As it was expected, the Verilog-A based simulations appeared to be quite inferior in CPU time compared to the equivalent simulations based on the hard-coded models. The reason is the fact that the present Verilog-A interfaces (including one in Spectre) are only interpreters of the Verilog-A language. It is likely that this deficiency will disappear in the future with the introduction of Verilog-A translators and/or compilers (3). Perhaps, the most important question related to the Verilog-A implementation of Mextram 504 is the achieved accuracy of the simulated electrical characteristics. To this end, the hard-coded implementation of Mextram 504 in Agilent circuit simulator ADS has been used as a reference for comparison. As a measure of the discrepancy between two model implementations, we have considered the relative error of simulated electrical characteristics. Since only the computational accuracy has been analyzed, the comparison has been based on the standard setups for Mextram model parameters extraction and the default values of the model parameters (4). Fig. 1-6 show the comparisons of various electrical characteristics obtained by Verilog-A Mextram 504 (dot lines) implementation, hard-coded Mextram 504 (solid lines) implementation and the corresponding relative error. It has been observed that in most cases the relative error of electrical characteristics used in our comparisons is quite low with the worst case of . Only the first point in both forward and reverse Gummel characteristics (Figs. 3 and 4) will exceed 1% due to convergent problems. The source of < 1% discrepancies could be the numerical accuracy of the variables and functions within the Verilog-A interpreter (in comparison to C double precision variables and functions), and the order in which the expressions are executed (especially in the symbolic evaluation of. Jacobian derivatives). 1% ≈